The present invention relates to a semiconductor device having a thyristor structure comprising four layers alternately different in conductivity types and further having two MISFETs for turning on/off purposes.
The parent U.S. patent application Ser. No. 08/218,200 discloses a semiconductor device having a thyristor structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type and a fourth semiconductor region of the second conductivity type, and further having a first MISFET for making majority carriers injectable into the second semiconductor region and a second MISFET capable of being turned on and off independently of the first MISFET and of extracting the majority carriers from the third semiconductor region, the fourth semiconductor region being divided into the source region of the first MISFET, and the source region of the second MISFET formed in a portion isolated from the source region of the first MISFET.
More specifically, as shown in FIG. 2, a p.sup.+ -type (first conductivity type) semiconductor substrate provided with a collector electrode (anode electrode) 1 on its undersurface, is a collector layer (first semiconductor region) 2, and an n.sup.- -type (second conductivity type) base layer (second semiconductor region) 3 is epitaxially grown on the collector layer 2. In this case, an n.sup.+ -type buffer layer may be provided between the collector layer 2 and the base layer 3. Moreover, a base layer (third semiconductor region) 4 in the form of a p-type well is formed by diffusion on the surface of the n.sup.- -type base layer 3. Further, a first emitter layer 51, a second emitter layer 52 and a drain layer 6, all of which are independent of each other and in the form of an n.sup.30 -type well, are formed on the inside surface of the p-type base layer 4. Of these layers, the n.sup.30 -type emitter layers 51 and 52 in a fourth semiconductor region are mutually connected via emitter electrodes 71 and 72, and a short-circuiting electrode 8 is straddlingly connected to the p-type base layer 4 and the n.sup.+ -type drain layer 6. Further, a first gate electrode 10 of polycrystal silicon forming a first MOSFET 12 is installed via a gate oxide film 9 over the surface extending from the first n.sup.30 -type emitter layer 51 to the p-type base layer 4 and further to the n.sup.- -type base layer 3. On the other hand, a second gate electrode 11 of polycrystal silicon forming a second MOSFET 13 is installed via the gate oxide film 9 over the surface extending from the n.sup.30 -type drain layer 6 to the p-type base layer 4 and further to the second n.sup.30 -type emitter layer 52. The first and second gate electrodes 10 and 11 are made separately controllable. The first and second MOSFETs 12 and 13 are n-channel MOSFETs.
FIG. 3 shows an equivalent circuit of the semiconductor device of FIG. 2. In this device, the first n.sup.30 -type emitter layer 52, the p-type base layer 4 and the n.sup.31 -type base layer 3 constitute an npn-type transistor Q.sub.npn1, the second n.sup.30 -type emitter layer 51, the p-type base layer 4 and the n.sup.- -type base layer 3 constitute an npn-type transistor Q.sub.npn2. Further, the p-type base layer 4, n.sup.- -type base layer 3 and the p+ collector layer 2 constitute an pnp-type transistor Q.sub.pnp. Consequently, the thyristor structure is formed with these transistors Q.sub.npn1, Q.sub.npn2, which are connected in parallel with each other and the emitter layers of which are different from each other, and Q.sub.pnp. With respect to these transistors Q.sub.npn1, Q.sub.npn2 and Q.sub.pnp, the first MOSFET 12 connects the n.sup.- -type base layer 3 as the collector of the transistor Q.sub.npn1 and the first emitter layer 51 via the p-type base layer 4, and injects electrons into the n-type base layer 3. On the other hand, the second MOSFET 13 connects the drain layer 6 and the second emitter layer 52, and extracts holes from the base layer 4.
When the first gate electrode 10 is set at a positive potential while the second gate electrode 11 is set at zero in potential or at a negative potential in the semiconductor device thus constructed, the surface of the p-type base layer 4 as the back gate of the first gate electrode 10 becomes an n-type inverted layer, whereby the emitter electrode 71, the n-type emitter layer 51 as the source, the n-type inverted layer beneath the first gate electrode 10 and the n.sup.- -type base layer 3 as the drain are thus connected. Consequently, electrons are injected into the n.sup.- -type base layer 3 as a drift region from the emitter electrode 71, and holes are also injected from the p.sup.+ -type collector layer 2 accordingly. This means the pnp-type transistor Q.sub.pnp is turned on. Further, as the hole current of the pnp-type transistor Q.sub.pnp becomes the base current of the transistors Q.sub.npn1 and Q.sub.npn2, the transistors Q.sub.npn1 and Q.sub.npn2 are turned on. In other words, the thyristor constituted by the p.sup.+ -type collector layer 2, the n.sup.- -type base layer 3, the p-type base layer 4 and the n.sup.30 -type emitter layers 51 and 52 is turned on. This device thus comes to have a low resistance as the high concentration carriers are caused to exist in the device. Thus, the device becomes a power device with a low ON-voltage because it is kept in the thyristor state by setting the first gate electrode 10 at a high potential while that of the second gate electrode 11 is kept at a low potential.
When the potential of the second gate electrode 11 is rendered high while the potential of the first gate electrode 10 is kept high in this ON state, the second MOSFET 13 is also turned on and the surface of the p-type base layer 4 beneath the second gate electrode 11 is inverted to the n-type. As the holes in the p-type base layer 4 are converted into electrons in the short-circuiting electrode 8, the p-type base layer 4, the short-circuiting electrode 8, the n.sup.30 -type drain layer 6, the n-type inverted layer beneath the second gate electrode 11 and the n.sup.30 -type emitter layer 52 are made conductive. For this reason, the hole current injected from the p-type collector layer 2 is to electron current through the p-type base layer 4 and the short-circuiting electrode 8 and flows out into the emitter electrode 72. Therefore, the npn-type transistors Q.sub.npn1 and Q.sub.npn2 are turned off. As a result, the thyristor function is eliminated and there follows the transistor state in which only the pnp-type transistor Q.sub.pnp operates. This state is similar to the operating state of IGBT and equivalent to a state in which the density of carriers existing in the device has decreased. Thus, when the potential of the first gate electrode 10 is then made negative to turn off, the time required for sweeping out the carriers can shortened, so that the turn-off time can be shortened.
This semiconductor device features that it is capable of not only performing a high-speed switching operation at a low voltage but also processing a large latchup current in the transistor state by separating the main current passage in the thyristor state from that in the transistor state. Since its second emitter layer 52 functions as the cathode of the thyristor in the thyristor state of the device, the main current linearly flows from the portion beneath the second emitter layer 52 as the source region of the second MOSFET toward the p.sup.+ -type collector layer 2. In the transistor state of the device, on the other hand, the majority carrier in the n-type base layer 3 passes through the first MOSFET and flows out toward the emitter electrode 71 connected to the first emitter layer 51 as the source region, whereas the minority carrier flows into the p-type base layer 4 from the first MOSFET side and flows out from the second emitter layer 52 toward the side of the emitter electrode 72 via a connection portion to the n.sup.30 -type drain layer 6 and the second MOSFET. Therefore, the main current passage in the thyristor state in the portion beneath the second emitter layer 52 as the source region of the second MOSFET, is not commonly used. In other words, the latchup is suppressed as the current passage in the transistor state remains to have a low resistance and a large current can thus be processed. Moreover, high stability is secured in the transistor state.